The present invention relates generally to a receiver built in a potable radio terminal for use in a radio communication system, and a radio communication system using the same. More specifically, the invention relates to a small receiver having a function of removing a direct current offset (which will be hereinafter referred to as a xe2x80x9cDC offsetxe2x80x9d if necessary), which is an undesired DC component produced in a direct conversion receiving system or a superheterodyne receiving system, and a radio communication system using the same.
In recent years, with the rapid progress of radio communication systems, it has been greatly required to decrease the size and price of radio terminals. As a receiving system complying with such a request, the direct conversion receiving system has been attracted. Referring to the drawings, the construction and operation principle of a direct conversion receiver will be described below.
FIG. 1 shows a basic construction of a direct conversion receiver. A high frequency signal received by an antenna 2 of a receiving section 1 is amplified by a RF amplifier 11 in an analog signal processing circuit 10, and then, divided into signals of two lines. The signals of two lines are mixed with carrier waves, which are supplied from a local oscillator 18 and which have substantially the same frequency as that of the received signal, by means of mixers 16 and 17, respectively, and then, directly frequency-converted into base frequency bands (base bands). The local oscillator 18 is directly connected to the mixer 16, and connected to the mixer 17 via a xcfx80/2 phase-shifter 19. Therefore, the signals of two lines frequency-converted into the base bands have phases shifted by xcfx80/2 from each other. The base band signals of two lines pass through low-pass filters (each of which will be hereinafter simply referred to as a xe2x80x9cLPFxe2x80x9d) 22 and 23 serving as channel selectors to remove undesired frequency components, respectively. Thereafter, the base band signals are amplified to desired signal levels by means of base band amplifiers 26 and 27, respectively. Then, the amplified base band signals are analog-to-digital converted by means of an analog/digital (which will be hereinafter simply referred to as an xe2x80x9cA/Dxe2x80x9d) converted 3, and then, demodulated to original data by means of a digital signal processing circuit 40 serving as detection/demodulation means.
In this direct conversion receiving system, since the received signals are directly frequency-converted into the base bands, there is no intermediate frequency, and there is no image response in theory. Therefore, there is an advantage in that it is not required to provide a very steep filter for removing image although such a filter is essential to the superheterodyne system. In addition, since the LPFs 22 and 23 for channel selection can be formed as large scale integrated circuits (LSIs), there is an advantage in that it is possible to decrease the size and price of receivers with the rapid progress of LSIs in recent years.
Although the direct conversion receiving system is suitable to decrease the size and price, there are the following problems. Referring to FIGS. 2A and 2B, such problems will be described below.
In FIG. 2A, a reference carrier wave necessary for the frequency conversion in the mixer 16 (or 17) is supplied from the local oscillator 18. Although it is desired that the isolation between the local port 16a and the RF port 16b of the mixer 16 is infinity, it is about 30 dB in fact. Therefore, the reference carrier wave inputted from the local port 16a is leaked toward the RF port 16b, and a part thereof is reflected on the output side of the RF amplifier 11 to be a reflected wave 32 to be inputted to the mixer 16 again. Alternatively, the part of the leaked reference carrier wave passes through the RF amplifier 11 to be leaked into the antenna 2 to be emitted from the antenna 2 to the outside as shown by reference number 34, and then, reflected on a reflector 36 to be inputted to the antenna 2 again to be a reflected wave 35 which is inputted to the mixer 16 again. In the mixer 16, these reflected waves 32 and 35 are mixed with the reference carrier waves outputted from the local oscillator 18 (self mixing). Since the reflected waves 32 and 35 have the same frequency as that of the reference carrier wave, the reflected waves appear as direct current output components (which will be hereinafter referred to as xe2x80x9cDC offsetxe2x80x9d) in the output of the mixer 16 by the self-mixing.
FIG. 2B shows such a DC offset on the axis of frequency. That is, in the direct conversion system, since a desired wave is frequency-converted into a base frequency band containing a DC component by nature, a DC offset component 7 produced by reflection is suppressed on a desired wave 6. It is known that the DC offset of this type causes the deterioration of receive error rate particularly in delay detection. As a ratio of D (=desi red wave) to U (=DC offset component) (which will be hereinafter referred to as xe2x80x9cD/Uxe2x80x9d) in order to obtain a desired receiver error rate, it is required to attenuate the DC offset component, for example, until about 20 to 30 dB can be obtained. However, the reference carrier wave supplied from the local oscillator 18 usually has about 0 dBm, so that the produced reflected waves 32 and 35 usually have a higher level than a desired wave level to be received by nature. Therefore, it is required to provide means for removing only the DC offset component on the output side of the mixer 16 in order to obtain a desired D/U.
As an example of conventional methods for removing the DC offset, there is a method using AC coupling means (which will be hereinafter referred to as an xe2x80x9cAC couplexe2x80x9d) 30 and 31 in the output of the mixers 16 and 17, as shown in FIG. 1. This method is effective when the DC offset is always constant. However, when the DC offset fluctuates with time, there is the following problem. FIG. 3(a) shows the output of the mixer 16 having no AC couple when a DC offset 104 is superposed on a desired wave 108. It is assumed that the DC offset 104 is changed to a DC offset 105 at time txe2x80x2 103. This corresponds to the fact that the circuit operation conditions of the RF amplifier 11 in FIG. 2A is changed. For example, this corresponds to the fact that the output impedance of the RF amplifier 11 varies to allow the reflected mount 32 to fluctuate in a case where the gain of the RF amplifier 11 is switched at time txe2x80x2 103 on the basis of a control signal 33 outputted from the digital signal processing circuit 4.
At the time, a difference 106 between the DC offset 104 before time txe2x80x2 103 and the DC offset 105 after time txe2x80x2 103 in FIG. 3(a) causes the fluctuation of DC offset. In such a case, the state that the AC couple 30 is applied to the output of the mixer 16 is shown in FIG. 3(b). That is, a transient response 109 corresponding to a time constant of a AC couple 30 occurs over a period of time 107 under the influence of the difference 106 of DC offsets. When a signal to be received incomes before the transient response 109 falls, the desired wave is under the influence of the DC offset, so that the deterioration of the receive characteristic occurs. That is, even if the AC couple 30 is used, the influence of DC offsets can not be removed. In addition, in a case where the AC couple 30 is used, a part of the desired wave is removed with respect to a desired signal containing a DC component as shown in FIG. 3(b) by the frequency characteristic 8 of the AC couple shown in FIG. 2B, so that there is a disadvantage in that the receive characteristic is deteriorated.
The aforementioned method for providing means for switching the gain of the RF amplifier 11 is often used in order to increase the receive dynamic range particularly n a direct conversion receiver. In addition, this method is usually used in order to prevent the useless consumption of a battery in a small receiver. Since such a battery saving control for a RF circuit also changes the operation condition of the circuit, the same fluctuation of DC offset occurs. Therefore, it is necessary for a small receiver, particularly for a direct conversion receiver, to prevent the influence of the aforementioned fluctuation of DC offset.
As can be seen from the above descriptions, the rate of fluctuation of a DC offset generally corresponds to the rate of fluctuation of a reflected wave inputted to the mixer 16 again. This was explained mainly with respect to the reflected wave 32 from the RF amplifier 11 in FIG. 1. On the other hand, in FIG. 2A, in a case where a wave radiated from the antenna 2 is reflected on the reflector 36 to be inputted to the mixer 16 again, the amount of DC offset in the output of the mixer 16 also fluctuates in accordance with the rate of the change of state of the outside reflector 36. For example, in a case where the outside reflector 36 is a moving vehicle, the amount of DC offset varies at the same rate as a fading pitch produced on the basis of the moving speed.
This situation is shown in FIGS. 4(a) and 4(b). In FIG. 4(b), reference number 111 denotes a TDMA frame, which periodically receives received slots 112 and 116 periodically assigned to their terminals. FIG. 4(a) shows DC offsets, and reference number 105 denotes a relatively high-speed fluctuation of DC offset produced in accordance with the fading pitch. On the other hand, reference numbers 113 and 114 also denotes DC offsets, which are relatively slow fluctuated components of DC offsets which are changed by carrying out the battery saving or the gain switching at time txe2x80x2 103. Therefore, in the direct conversion receiver under an actual environment, the high-speed fluctuation of DC offset is mixed with the low-speed fluctuation of DC offset. For that reason, for practical use, it is desired to more flexibly remove the influence of the fluctuation of DC offset in accordance with the cause of DC offset and the temporal fluctuation of DC offset.
In addition, the same problems as the aforementioned problems with the respect to the fluctuation of DC offset occur, not only in the aforementioned zero IF receiver, also in so-called superheterodyne receiving system shown in FIG. 5, wherein a received frequency is frequency-converted into an intermediate frequency, and then, frequency-converted into a base band again. That is, FIG. 5 shows a basic construction of a receiver having an analog orthogonal demodulating section. In this receiver, a high-frequency signal received by a receiving section 1 containing antenna 2 is amplified by the RF amplifier 11. This signal is frequency-converted into an intermediate frequency by means of a frequency-converting section 12.
That is, the high-frequency signal is multiplied by a reference signal outputted from a local oscillator 13, by means of a mixer 14 of a frequency converting section 12, and the wide-area components produced by the multiplication is removed by a band-pass filter (BPF) 15. Thereafter, the received signal frequency-converted into an intermediate frequency by means of the frequency converting section 12 is divided into signals of two lines. Then, these signals are mixed with carrier waves, each of which has substantially the same frequency as that of an intermediate frequency signal supplied from the local oscillator 18, by means of the mixers 16 and 17 to be frequency-converted (orthogonal-demodulated) into a base frequency band. The local oscillator 18 is connected to the mixer 16 and also connected to the mixer 17 via the xcfx80/2 phase-shifter 19. Therefore, the signals of two lines frequency-converted into the base band have phases shifted by xcfx80/2 from each other. From these base band signals of two lines, undesired frequency components other than desired channels are removed by low-pass filters (LPFs) 22 and 23 serving as channel selectors. Thereafter, these signals are amplified to desired signal levels by base-band amplifiers 26 and 27, and then, A/D converted by the A/D converter 3 to be demodulated to original signals by a detector built in the digital signal processing circuit 4. Furthermore, although it is required to provide an image removing filter down-stream of the RF amplifier 11, the description of this filter will be omitted hereinafter.
The operation of the superheterodyne receiver having the construction shown in FIG. 5 is the same as that of the aforementioned zero IF receiver. Therefore, there are the same problems as those of the temporal fluctuation of DC offset, which have been described referring to FIGS. 2 through 4.
In addition, in the aforementioned receiver having the orthogonal demodulating section and the zero IF receiver, it is required to switch the gain of the radio section. Referring to FIGS. 6 through 10B, examples of conventional methods for switching the gain will be described. FIG. 6 shows an example of a conventional zero IF receiver, to which a method for switching the gain of a radio section is applied. In FIG. 6, an analog signal processing circuit 10A has the same construction as that of the analog signal processing circuit 10 of FIG. 1, except that the AC couples 30 and 31 are not provided. In FIG. 6, the radio section is, e.g., the analog signal processing circuit 10A including a RF amplifier 11, mixers 16 and 17 and amplifiers 26 and 27.
In FIG. 6, and IQ signal 117 upstream of a detector 36 is picked up to be inputted to an intensity detecting/comparing circuit 37 for detecting and comparing the received field intensity. The received field intensity is calculated by means of the intensity detecting/comparing circuit 37 to be compared with a reference voltage 38. Thus, optimum gains to be set in the RF amplifier 11, the mixers 16, 17 and the amplifiers 26, 27 are determined to output gain control signals 121. That is, gain control signals 118, 119 and 120 are supplied to the RF amplifier 11, the mixer 16, 17 and the amplifiers 26, 27. The gain switching control is carried out by setting the gains of the respective circuits in accordance with the received field intensity, e.g., as shown in the table of FIG. 7. In FIG. 7, five receive modes including modes A through E are provided by combining the gains of the radio section so that a receive dynamic range of 100 dB can be ensured.
However, in a case where the radio-section gain switching shown in FIG. 6 is carried out, there is the following problem particularly with respect to DC offsets. Referring to FIGS. 8A through 9B, this problem will be described. FIGS. 8A through 9B show only one channel of the IQ channels of the zero IF receiver of FIG. 6. It will be now described that the DC offset output of the mixer 16 fluctuates by switching the gain of the RF amplifier 11. FIG. 8A shows the state of mode E in FIG. 7, i.e., the state that the gain of the RF amplifier 11 is set to be 0 dB. On the other hand, FIG. 9A shows the state of mode D, i.e., the state that the gain of the RF amplifier 11 is set to be 20 dB. It is assumed that the gain of the RF amplifier 11 is switched from the state of FIG. 8A to 20 dB of FIG. 9A (from mode E to mode D in FIG. 7) by a RF-amplified gain switching control signal 118 outputted from a control section (not shown).
At this time, with respect to the amount of a wave reflected on the RF amplifier 11 after outgoing the local oscillator 18 to pass through the mixer 18, the amount of a reflected wave 124 of FIG. 7A is different from that of a reflected wave 125 of FIG. 9A. Because the output impedance of the RF amplifier 11 of FIG. 8A is different from that of FIG. 9A. In both cases of FIGS. 8A and 9A, a direct current (DC) component produced by the self-mixing is superposed on a desired signal component 123 to produce a mixer output 122. For the aforementioned reason, a mixer DC output DCLOW in FIG. 8 is different from a mixer DC output DCHIGH in FIG. 9A. Therefore, when the gain of the RF amplifier 11 is switched from 0 dB (the state shown in FIG. 8B) to 20 dB (the state shown in FIG. 9B) (from mode E to mode D in FIG. 7), a fluctuation of DC offset being a difference between DCLOW and DCHIGH occurs at the output of the mixer 16.
As mentioned above, even if the gain of the mixer 16 is constant (the changed component of the gain of the mixer when the mode is switched from mode E to mode D=0 dB), the fluctuation of DC offset occurs at the output of the mixer 16 in accordance with the switching of the gain of the RF amplifier 11.
The aforementioned phenomenon that the DC offset output fluctuates does not always occur only when the gain of the RF amplifier 11 is changed. Similar to the gain change of the RF amplifier 11, the fluctuation of DC offset occurs by the change of the gains of the mixer 16 and the amplifier 26. Moreover, in circuits having different gains, the output DC components of the respective circuits are different from each other, so that the fluctuation of DC offset occurs when the gain of the circuit is switched.
If such a fluctuation of DC offset occurs during a call, it is required to very quickly correct the fluctuation of DC offset. Referring to FIGS. 10A and 10B, this aspect will be described. FIG. 10A shows a received time slot of TDMA, and FIG. 10B is an enlarged view of the received time slot. In FIG. 10A, T denotes a TDMA frame length. After a received time slot 126 assigned to its terminal is received in mode E of FIG. 7, the mode is changed to mode D at a gain switching timing 129, and it is considered to receive the next slot 127. The DC offset is changed from D to E at the gain switching timing 129. In a case where the DC offset is corrected, it is required to correct the DC offset before the starting time 180 of the received time slot. However, in a system having a very short frame length T, a desired operation time may be unavailable. Moreover, as shown in FIG. 10B, in a case where it is required to carry out the gain switching of modes A, B, C, D and E of the received time slot 127 assigned to its terminal, it is required to instantaneously correct the DC offset. In a case where the DC offset can not be instantaneously corrected, the DC offsets A, B, C, D and E in the respective receive modes are different from each other as shown in FIG. 10B. Therefore, the fluctuated component of DC offset is superposed on a desired signal, so that the receive characteristic is greatly deteriorated.
In addition, in conventional direct conversion receivers, the LPFs 18 and 19 can be formed as LSIs. However, due to the dispersion of cut off frequencies based on the dispersion of elements formed as LSIs, the channel selection can not be sufficiently carried out, and desired signals may be removed, so that the receive characteristic may be deteriorated.
As mentioned above, in conventional direct conversion receivers, there is a problem in that the receive error rate is deteriorated by the DC offset produced when the received signal is processed by the analog signal processing circuit. In addition, in superheterodyne receivers, there is also a problem in that the receive error rate is lowered by the temporal fluctuation of the DC offset.
In addition, there is a disadvantage in that, even if it is tried to remove the DC offset by only the AC couple, it is not possible to completely remove the influence of the DC offset due to the transient response in the AC couple when the temporal fluctuation of DC offset occurs. Moreover, since the AC couple removes a part of signal components with respect to received signals having DC signal components, the receive characteristic may be deteriorated by removing the part of the signal components, so that there is a disadvantage in that the offset removing function can not be sufficiently provided by only providing the AC couple in the analog signal processing section.
In addition, there is a disadvantage in that a good call can not be accomplished by a system using such a receiver, since the receive error rate is deteriorated due to the DC offset produced when the signal thus received is processed by the analog signal processing circuit.
In addition, in a conventional receiver having an orthogonal demodulating section, there is a problem in that the receive characteristic is deteriorated by the DC offset produced in the analog signal processing section. In addition, although the DC offset may be detected to be corrected, there is a problem in that the detection and correction of the DC offset take a lot of time. Therefore, in a case where the amplitude of the receive level is rapidly changed or in a case where the receive level is indefinite, there is a problem in that it is not possible to respond to the fluctuation of the DC offset produced when the gain of the required radio section is quickly switched.
In addition, there is a problem in that the receive characteristic is deteriorated by the dispersion in cut off frequency of the filter formed as a LSI. Due to the DC offset produced when the signal thus received is processed by the analog signal processing circuit and due to the deterioration of the receive error rate caused by the dispersion in cut-off frequency of the filter, there is a problem in that a good call can not be accomplished by a system using such a receiver.
Moreover, in a case where the DC offset is detected, if a signal wave having a DC component other than the DC offset to be detected is received, the DC offset can not be accurately detected. Therefore, if a radio wave used for another radio communication system is received by an antenna, there is a possibility in that the DC offset can not be accurately detected due to the incoming wave.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a receiver, which can accurately remove the DC offset in accordance with the temporal fluctuation of DC offset produced in an analog processing section, and a communication system using the receiver.
In order to accomplish the aforementioned and other objects, according to a first aspect of the present invention, a receiver comprises: a receiving section for receiving a radio frequency signal; an analog signal processing section for amplifying, band-converting and frequency-converting an analog signal inputted from the receiving section; an AD converting section for converting an output of the analog signal processing section from an analog signal to a digital signal; a digital signal processing section for processing the digital signal converted by the DC converting section; offset detecting means, provided in the digital signal processing section, for detecting a direct current offset signal produced in the receiving section or a frequency converting section; offset holding means, provided in the digital signal processing section, for holding the direct current offset signal detected by the offset detecting means; a DA converting section for converting the direct current offset signal detected by the digital signal processing section into an analog signal; and first offset correcting means, provided in the analog signal processing section, for correcting the analog signal on the basis of the direct current offset signal converted by the DA converting section into the analog signal.
According to a second aspect of the present invention, a receiver further comprises second offset correcting means for digitally decreasing a part of the direct current offset signal held by the offset holding means to decrease the direct current offset.
According to a third aspect of the present invention, there is provided a receiver wherein the direct current offset held by the offset holding means is updated every time the offset detecting means detects an offset.
According to a fourth aspect of the present invention, a receiver further comprises offset distributing means for correcting at least an offset part exceeding a predetermined threshold by the first offset correcting means when an absolute value of an offset detected by the offset detecting means exceeds the predetermined threshold.
According to a fifth aspect of the present invention, there is provided a receiver wherein the predetermined threshold is a power of 2.
According to a sixth aspect of the present invention, there is provided a receiver wherein more significant bite of the offset held by the offset holding means are converted into analog values by means of the DA converting section to correct the offset by the first offset correcting means, and less significant bits of the offset held by the offset holding means are used to correct the offset by the second offset correcting means.
According to a seventh aspect of the present invention, there is provided a receiver wherein the offset holding means comprises first storing means for holding at least an initial value of the offset detected by the offset detecting means, and second storing means for holding a fluctuated part of an offset varying with time, the fluctuated part being detected by the offset detecting means after the offset is corrected on the basis of the initial value of the offset by the first and second offset correcting means.
According to a eight aspect of the present invention, there is provided a receiver wherein the initial value of the offset stored in the first storing means is detected by the offset detecting means only once, and thereafter, the detected initial value is unchanged.
According to a ninth aspect of the present invention, there is provided a receiver wherein the initial value of the offset stored in the first storing means is detected to be set when a power supply is turned on.
According to a tenth aspect of the present invention, there is provided a receiver wherein the initial value of the offset stored in the first storing means is detected every time a predetermined period of time elapses.
According to an eleventh aspect of the present invention, there is provided a receiver wherein the initial value of the offset stored in the first storing means is updated when the fluctuated part of the offset varying with time exceeds a predetermined value.
According to a twelfth aspect of the present invention, there is provided a receiver wherein the fluctuated part of the offset stored in the second storing means is corrected by the second offset correcting means provided in the digital signal processing section.
According to a thirteenth aspect of the present invention, there is provided a receiver wherein the initial value of the offset stored in the first storing means is corrected by the first offset correcting means provided in the analog processing section, and the fluctuated part of the offset stored in the second storing means is corrected by the second offset correcting means provided in the digital signal processing section.
According to a fourteenth aspect of the present invention, a receiver further comprises: means for measuring a received field intensity inputted via the signal input section; means for setting a plurality of gains in the analog signal processing section on the basis of the received field intensity; the offset detecting means detecting a plurality of direct current offset values produced in accordance with the plurality of gains set in the analog signal processing section; the offset holding means holding the plurality of direct current offset values; and the first offset correcting means reading a direct current offset value, which corresponds to a gain set in the analog signal processing section, out of the offset holding means to correct the direct current offset.
According to a fifteenth aspect of the present invention, there is provided a receiver wherein the analog signal processing section comprises: a pair of mixers for frequency-converting signals perpendicular to each other containing at least an in-phase component and an orthogonal component of the radio frequency signal inputted to the signal input section; and base band filters provided in an in-phase component channel and an orthogonal component channel which are outputs of the pair of mixers, the first offset correcting means being provided at least upstream of the base band filters for correcting the direct current offset produced in the analog signal processing section.
According to a sixteenth aspect of the present invention, there is provided a receiver wherein the analog signal processing section is set to be a first gain value, and the AD converting section converts an output of the analog signal processing section into a digital value, the receiver further comprising: a overflow detecting circuit for detecting an overflow state of the AD converting section; and control means for controlling the gain of the analog signal processing section so that the gain is set to be a second gain value smaller than the first gain value when the overflow state is detected by the overflow detecting circuit.
According to a seventh aspect of the present invention, there is provided a receiver wherein the analog signal processing section includes storing means for detecting and storing a direct current offset produced by the inputted radio frequency signal, and the first offset correcting means corrects the direct current offset on the basis of the first gain value read out of the storing means even if only one receive is carried out.
According to an eighteenth aspect of the present invention, a receiver further comprises analog signal no-input means for no-inputting the analog signal inputted to the analog signal processing section, and wherein the offset detecting means detects the direct current offset when the analog signal is no-inputted, and the first offset correcting means corrects the direct current offset on the basis of the detected direct current offset value.
According to a nineteenth aspect of the present invention, there is provided a receiver wherein the analog signal no-input means comprises a switch provided between a radio frequency signal amplifier provided in the analog signal processing section and the signal input section.
According to a twentieth aspect of the present invention, there is provided a receiver wherein the analog signal no-input means comprises: attenuator connected in parallel to the radio frequency signal amplifier provided in the analog signal processing section; four switches provided upstream and downstream of each of the amplifier and the attenuator; and a fifth switch provided in a connecting line upstream of the amplifier and the attenuator, and wherein a signal supply path extending from the signal input section and the analog signal processing section is capable of causing the analog signal processing section to be in a no-input state even of the signal supply path is always connected.
According to a twenty-first aspect of the present invention, there is provided a receiver wherein the offset detecting means detects the direct current offset by a time mean of outputs of the AD converting section, and the first offset correcting means corrects the direct current offset by subtracting the direct current offset, which is converted into an analog signal by means of the DA converting section, from the analog signal processed by means of the analog signal processing section.
According to a twenty-second aspect of the present invention, there is provided a receiver wherein the offset detecting means detects the direct current offset on the basis of the received slot in a time division multiple connection system, and the first offset correcting means corrects the direct current offset on the basis of the detected value of the direct current offset detected by the received slot.
According to a twenty-third aspect of the present invention, there is provided a receiver wherein the offset detecting means detects a direct current offset of the current received slot using, as an initial value, a time mean value of direct current offsets detected by the past received slots, and the first offset correcting means corrects the detected direct current offset of the current received slot.
According to a twenty-fourth aspect of the present invention, there is provided a receiver wherein the offset detecting means comprises: a cumulating/adding circuit for cumulating/adding digital signals inputted from the AD converting section; and a divider circuit for dividing the cumulated/adding signals, and wherein the offset holding means comprises; a plurality of delay circuits for delaying outputs of the offset detecting means by a predetermined period of time; a plurality of weighting circuits for multiplying the values, which are delayed by means of the delay circuits, by weighting coefficients, which are preset so as to increase as approaching the direct current offset, to output the multiplied values; and an adder circuit for integrating outputs of the weighting circuit to output the integrated value as a direct current offset value.
According to a twenty-fifth aspect of the present invention, there is provided a receiver wherein each of the weighting coefficients of the plurality of weighting circuits is set so that the older weighting coefficient is light and the newer weighting coefficient is heavy.
According to a twenty-sixth aspect of the present invention, there is provided a receiver wherein each of the weighting coefficients set in the plurality of weighting circuits varies in accordance with the fluctuating amount of the direct current offset which is detected by the offset detecting means and which fluctuates with time.
According to a twenty-seventh aspect of the present invention, there is provided a receiver which has a test mode in which a band limitation characteristic of the analog signal processing section is tested, wherein the digital signal processing section comprises: a generator for generating a test signal for testing the band limitation characteristic of the analog signal processing section; and an adder for adding the test signal, which is outputted from the test signal generator in the test mode, to the direct current offset signal, and wherein the first correcting means supplies an output of the adder after being converted into an analog signal by means of the DA converting section, to an input of a band limitation circuit of the analog signal processing section.
According to a twenty-eighth aspect of the present invention, there is provided a receiver wherein the analog signal processing section tests the band limitation characteristic in the analog signal processing section after the direct current offset is detected by the offset detecting means and the direct current offset is held by the offset holding means.
According to a twenty-ninth aspect of the present invention, there is provided a receiver wherein the analog signal processing section has a band limitation circuit having a function of adjusting the band limitation characteristic of the analog signal, and the digital signal processing section has a frequency characteristic control means for producing the frequency characteristic control signal in accordance with a difference between a frequency characteristic detected by the test signal supplied to the band limitation circuit in the test mode end a desired frequency characteristic.
According to a thirtieth aspect of the present invention, a communication system comprises: a transmitter for transmitting a radio frequency signal of an information signal containing voice and image; a communication network for transmitting and receiving the radio frequency signal; and a receiver having a function of a direct current offset, the receiver comprising: a receiving section for receiving the radio frequency signal; an analog signal processing section for amplifying, band-converting and frequency-converting an analog signal inputted from the receiving section; an AD converting section for converting on output of the analog signal processing section from an analog signal to a digital signal; and a digital signal processing section for processing the digital signal converted by the DC converting section; offset detecting means, provided in the digital signal processing section, for detecting a direct current offset signal produced in the receiving section or a frequency converting section; offset holding means, provided in the digital signal processing section, for holding the direct current offset signal detected by the offset detecting means; a DA converting section for converting the direct current offset signal detected by the digital signal processing section into an analog signal; and first offset correcting means, provided in the analog signal processing section, for correcting the analog signal on the basis of the direct current offset signal converted by the DA converting section into the analog signal.
According to the aforementioned communication system, since it is possible to decrease a DC offset, which is produced in the analog signal processing circuit, at the input of the A/C converter of the receiver, it is possible to a signal from being distorted by the DC offset in excess of the input range of the A/D converter and to decrease the receiver error rate, so that it is possible to achieve a good communication. In addition, since no AC couple is used, there is no influence of the transient response of the temporal variation of the DC offset. Therefore, it is possible to decrease the deterioration of the receive error rate, so that it is possible to achieve a good communication. Moreover, since it is possible to remove only DC offset components serving as errors to a signal used for a modulation system containing low-frequency components containing DC, it is possible to decrease the deterioration of the error rate of the received signal, so that it is possible to achieve a good communication.
In addition, with the aforementioned construction, even immediately after a call is started, it is possible to roughly offsets by storing the offset value only once when the power supply is turned on, so that it is possible to decrease the deterioration of the receive error rate.